It is well known that electrostatic discharge ("ESD") can damage an integrated circuit ("IC") during handling. Therefore, it is common to connect an ESD protection devices to the input/output ("I/O") pads of an IC to protect them from ESD damage.
During an ESD test, charges flow from an external capacitor to the I/O pads. In order to minimize the energy consumed by the ESD protection devices, the turn-on voltage of the ESD devices needs to be as low as possible. However, the turn-on voltage of the ESD protection devices has to be higher than the applied voltage Vcc during normal operation.
FIGS. 1a-1d illustrate examples of ESD protection devices as used in the semiconductor industry. FIG. 1a shows an input ESD device 10a consisting of an N-field transistor 12, a resistor 14, and a ground gate NMOS transistor 16a. During the ESD test, the N-field transistor 12 consumes most of the energy. The ground gate NMOS transistor 16a maintains the voltage low on the input buffer 18 to avoid damaging the input buffer 18.
In some cases, the field transistor can be replaced by a large NMOS transistor. In such a case, the ESD device consists of a large NMOS transistor, a resistor, and a small NMOS transistor.
Another variation of the ESD protection uses one NMOS transistor instead of two. FIG. 1b shows an NMOS transistor instead of two. FIG. 1b shows an NMOS transistor 16b with its gate grounded directly to Vss. FIG. 1c shows NMOS transistor 16b with its gate grounded through an inverter 20. A resistor may optionally be connected between the NMOS transistor 16b and the pad, shown in the figures as a dotted line connection. The NMOS transistor 16b needs to consume all of the ESD energy while maintaining a low voltage on the input buffer 18 during the ESD test.
In the case of output pad protection, active output devices also provide ESD protection. FIG. 1d shows a typical output buffer configuration with a pull-up MOS transistor 22 (either PMOS or NMOS) and a pull-down NMOS transistor 24 used for normal circuit operation and for ESD protection. This output structure can also be used for input ESD protection.
Lightly doped drains can be added to a standard process for fabricating source/drain regions by adding a low dose of phosphorus.
Cross-sectional views of a field transistor and an NMOS transistor are shown in FIGS. 2a and 2b, respectively. The N-region in both figures is provided by an LDD phosphorus implantation. Due to the gradual profile of phosphorus, breakdown voltages of an LDD N+/P- well junction and a ground gate NMOS are increased. This increases the initial turn-on voltage of these devices, which degrades the ESD protection capability of such devices. On the other hand, a lightly doped phosphorus dopant advantageously decreases the N+/P- well capacitance, thereby improving the speed of the device.
The present invention is directed to a semiconductor integrated circuit for use in an ESD protection circuit. A substrate has an active region formed therein so as to define a P/N junction therebetween. An insulating region is formed near the surface of the substrate adjacent the active region thus defining an edge therewith. The active region includes a highly doped portion formed near the surface of the substrate and near the edge of the insulating region and a lightly doped portion formed below the highly doped portion and separated from the edge of the insulating portion. By moving the lightly doped portion of the active region away from the insulating region, the P/N junction is effectively moved away from the insulating region.
A better understanding of the features and advantages of the present invention will be obtained by reference to the following detailed description of the invention and accompanying drawings which set forth an illustrative embodiment in which the principles of the invention are utilized.